The AD9760 and AD9760-50 are the 10-bit resolution members of the TxDAC series of high performance, low power CMOS digital-to-analog converters (DACs). The AD9760-50 is a lower performance option that is guaranteed and specified for 50 MSPS operation. The TxDAC family that consists of pin compatible 8-, 10-, 12- and 14-bit DACs is specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface options, small outline package and pinout, thus providing an upward or downward component selection path based on performance, resolution and cost. Both the AD9760 and AD9760-50 offer exceptional ac and dc
performance while supporting update rates up to 125 MSPS and 60 MSPS respectively.
The AD9760's flexible single-supply operating range of 2.7 V to 5.5 V and low power dissipation are well suited for portable and low power applications. Its power dissipation can be further reduced to a mere 45 mW without a significant degradation in performance by lowering the full-scale current output. Also, a power-down mode reduces the standby power dissipation to approximately 25 mW.
The AD9760 is manufactured on an advanced CMOS process. A segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. Edge-triggered input latches and a 1.2 V temperature compensated bandgap reference have been integrated to provide a complete monolithic DAC solution. Flexible supply options support +3 V and +5 V CMOS logic families.
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Communication Transmit Channel: Basestations Set Top Boxes Digital Radio LinkDirect Digital Synthesis (DDS)Instrumentation
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Member of Pin-Compatible TxDAC Product Family125 MSPS Update Rate10-Bit ResolutionExcellent Spurious Free Dynamic Range PerformanceSFDR to Nyquist @ 40 MHz Output: 52 dBcDifferential Current Outputs: 2 mA to 20 mAPower Dissipation: 175 mW @ 5 V to 45mW @ 3 VPower-Down Mode: 25 mW @ 5 VOn-Chip 1.20 V ReferenceSingle +5 V or +3 V Supply OperationPackages: 28-Lead SOIC and TSSOPEdge-Triggered Latches
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| Parameter |
With Respect to |
Min Max |
Units |
| AVDD |
ACOM |
0.3 +6.5 |
V |
| DVDD |
DCOM |
0.3 +6.5 |
V |
| ACOM |
DCOM |
0.3 +0.3 |
V |
| AVDD |
DVDD |
6.5 +6.5 |
V |
CLOCK, SLEEP
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DCOM |
0.3 DVDD +0.3 |
V |
| Digital Inputs |
DCOM |
0.3 DVDD +0.3 |
V |
| IOUTA, IOUTB |
ACOM |
1.0 AVDD +0.3 |
V |
| ICOMP |
ACOM |
0.3 AVDD +0.3 |
V |
| REFIO, FSADJ |
ACOM |
0.3 AVDD +0.3 |
V |
REFLO |
ACOM |
0.3 +0.3 |
V |
| Junction Temperature |
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+150 |
°C |
Storage Temperature |
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65 +150 |
°C |
| Lead Temperature(10 sec) |
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+300 |
°C |
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